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Altera_Forum's avatar
Altera_Forum
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12 years ago

Cannot resolve algebric loop

Developed a simulink model by importing VHDL design of FIR compiler II IP. I integrated a vhdl wrapper (to buffer the input data based on sink_valid and sink_ready) import to feed the input to the fi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Can you pls tell me how to submit this issue to Altera support online? I tried to go to "mySupport" then "Get Design & Support resources" then "mysupport" to create an service request. But it is not working out.