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Altera_Forum's avatar
Altera_Forum
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12 years ago

Cannot resolve algebric loop

Developed a simulink model by importing VHDL design of FIR compiler II IP. I integrated a vhdl wrapper (to buffer the input data based on sink_valid and sink_ready) import to feed the input to the fi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Unless someone has experienced this exact error, it's probably best if you submit a support request to Altera.

They will need your setup for both the working and failing designs to reproduce the issue, and will probably ask if you are running the latest version of the quartus tools. So if you can provide that with your support request information, it may save at least a few days of back and forth.

I also recommend if you have a local Altera FAE, you ask them, and have them help you bird-dog the issue through the support process.

Pete