Forum Discussion
This is for the Cyclone V. I have two boards really, a Terasic De10-Nano, and a CriticalLink Mitysom Cyclone V.
I have discovered that some of the parts I see are in the `intelFPGA/19.1/hld/ip/board/iface` directory. Some of these are the acl_kernel_clk.qsys, acl_kernel_interface_soc.qsys, etc.
Within these, the sub-systems use some of the standard IP, such as a Clock Bridge, Reset Bridge, etc, but some also use "ACL internal components", and I cannot find any documentation on those. Examples of these are:
- ACL Bank Splitter w. Reorder
- ACL Burst Boundary Splitter
- ACL irq ena
- ACL No Reset
And others.
These show up in "Platform Designer" under the IP Catalog, under "ACL Internal Components" -- but I'm not sure how that directory got added to my project, or where the information on it is.
I find that the actual documentation for the OpenCL implementation, form a Board Support Package, is really terrible -- I've spent weeks, several months even, trying to understand this stuff, and it's been very frustrating and difficult to navigate. I'd really appreciate a bit more detail on information about implementing a Board Support Package with OpenCL.