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Altera_Forum's avatar
Altera_Forum
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15 years ago

Can we separate the inout data bus PFL (parallel flash loader) IP core?

Hi, we are using the PFL ip core in MAX2 cpld to download the FPGA configuration file to flash and to program the ARRIA2 FPGA. we had a requirement to dowload the configuration file f...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Thank you for your reply.I edited the PFL core just to split the inout bus into seperate in and out busses and added the wrapper to it.

Regards,

Ramesh.B