Solved
Forum Discussion
Wujun
New Contributor
5 years agoThank you. Refer to the schematic, an I/O is connected to the End Port PCIe reset.
Hi ,
I will share you one design , I hope it is publicly available with Root port .
Use the below as reference
Kindly have reference.
https://rocketboards.org/foswiki/Projects/Stratix10PCIeRootPortWithMSI
Thank you. Refer to the schematic, an I/O is connected to the End Port PCIe reset.