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Wujun's avatar
Wujun
Icon for New Contributor rankNew Contributor
5 years ago
Solved

Can nPERST pins be used as PCIe reset if Intel® Stratix® 10 PCI Express* Hard IP is used as Root Complex?

Hello, According to the Pin Connection Guildline, Pin Functions of nPERST[L,R][0:2] are input or I/O. When you do not use this pin as the fundamental reset, you can use this pin as a user I/O pin. ...
Rahul_S_Intel1's avatar
Rahul_S_Intel1
Icon for Frequent Contributor rankFrequent Contributor
5 years ago

Hi ,

The pin_perst configured as input ?

>> Yes

From the screen shot, pin_perst is just an internal signal

>> Yes you are right, it is an internal signal . This internal signal pin_perst of each hard IP instance to the corresponding nPERST pin of the device. ( Reference pag no: 48) , also attaching the screen shot also for easy reference.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_s10_pcie_avst.pdf

Do you mean when S10 is setting as root port, nPERST pin can be used and be configured as output?

>> No

  • Wujun's avatar
    Wujun
    Icon for New Contributor rankNew Contributor
    5 years ago

    So how to control the PCIe reset? In this case, both Root port and End port are input signals. Connect a FPGA I/O pin with S10 nPERST and End Port PCIe reset?