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Altera_Forum's avatar
Altera_Forum
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10 years ago

can not understand the figure of High-Performance controller ?

http://www.alteraforum.com/forum/attachment.php?attachmentid=10313&stc=1 I can not understand the figure in "Chapter 3: Using High-Performance DDR, DDR2, and DDR3 SDRAM with SOPC Builder" ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

That's a glitch.. Probably caused by combinational logic after the last flip-flop in the data path to those signals.

If the signal was being used by a clock somewhere it would be an issue. But as long as it's stable before the next rising edge it should be ok for the date path. it's fine.