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gena's avatar
gena
Icon for New Contributor rankNew Contributor
6 years ago

Can not stop next concecutive rx_st_sop

Hello,
Can anyone in intel help to solve my following issue on pcie core?

I’m designing the PCIe add-in card that has intel FPGA, and using PCIe hard-ip core below.
-Cyclone10GX
-X4, gen1.1a
-Endpoint, Avalon-st
I’m debugging memory and register accesses through the pcie core on the card, by using our diagnostic software.
During debugging, I observed the following symptom on TLP data stream form the core.

Symptom:
Usually, there is no issue on rx_st_sop behavior.
However, by increasing TLP traffics, I observed that core has hold rx_st_sop asserted intermittently, even though user-logic does de-assert rx_st_ready.
Now my user-logic cannot handle TLP packet with this symptom.

I’d like to know if this is a normal behavior of the pcie ip core.
and I’d like to know how to sop next consecutive rx_st_sop in this case.

What do think?
Regards,

10 Replies

    • gena's avatar
      gena
      Icon for New Contributor rankNew Contributor
      6 years ago

      Hello,
      Yes, I’m using PCIe Avalon-ST interface and User logic for its control.

      • Rahul_S_Intel1's avatar
        Rahul_S_Intel1
        Icon for Frequent Contributor rankFrequent Contributor
        6 years ago

        Hi,

        I gone through the data base from our system of the issue reported from your side , I could not able to see any one have reported the same behaviour by increasing the TLP.

        For further issue debugging ,the issue have to replicate inhouse , that limitation is there