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gena's avatar
gena
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5 years ago

Can not stop next concecutive rx_st_sop

Hello, Can anyone in intel help to solve my following issue on pcie core? I’m designing the PCIe add-in card that has intel FPGA, and using PCIe hard-ip core below. -Cyclone10GX -X4, gen1.1a -E...
Rahul_S_Intel1's avatar
Rahul_S_Intel1
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5 years ago

To confirm you are using PCIe Avalon ST and User logic right

gena's avatar
gena
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5 years ago

Hello,
Yes, I’m using PCIe Avalon-ST interface and User logic for its control.

  • Rahul_S_Intel1's avatar
    Rahul_S_Intel1
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    5 years ago

    Hi,

    I gone through the data base from our system of the issue reported from your side , I could not able to see any one have reported the same behaviour by increasing the TLP.

    For further issue debugging ,the issue have to replicate inhouse , that limitation is there

    • gena's avatar
      gena
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      5 years ago

      Hello,

      Do you have any comments on the followings?
      -Possible root cause.
      -How to proceed to debug with the core.

      I’d like to have off-line communication regarding this symptom with intel.
      For further debugging, could you email me intel’s contact information or direct me to the person?

      Thank you.
      Regards,

      • Rahul_S_Intel1's avatar
        Rahul_S_Intel1
        Icon for Frequent Contributor rankFrequent Contributor
        5 years ago

        Taking in to private converstation