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Altera_Forum
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13 years ago

Can Avalon-ST Dual Clock FIFO's fifo depth exceed 32?

accroding to the spec <ug_embedded_ip>P15-4,the descriptions for parameter 'FIFO depth',legal value is ONLY 1~32. But when I use Qsys ver 12.0 to add the DC_FIFO component,I can type in '1024' to ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Thank you very much!

And yesterday when I use Qsys,type in '2000'to FIFO depth,it reminds me that "the FIFO depth has to be a power of 2."I think it may be a error in the doc or I confused it.