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Altera_Forum
Honored Contributor
Honored ContributorCan Avalon-ST Dual Clock FIFO's fifo depth exceed 32?
accroding to the spec <ug_embedded_ip>P15-4,the descriptions for parameter 'FIFO depth',legal value is ONLY 1~32. But when I use Qsys ver 12.0 to add the DC_FIFO component,I can type in '1024' to ...
Altera_ForumHonored Contributor
Honored ContributorThat's a documentation error. I don't know what the maximum is but I know it is much larger than 32. I've used 1k before so you should be fine with that setting.
