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corestar's avatar
corestar
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1 month ago
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Can an Application Ignore PCIe flow Control Credits?

I'm using a Cyclone V GT with PCIe core using Gen 1 Avalon-ST 64-bit endpoint interface. Occasionally packet sending would stall and I had thought it was because I was ignoring the flow control credi...
  • VenT_Altera's avatar
    9 days ago

    Hi corestar,


    My apologies on the delayed response.

    Yes, the flow control signal (tx_cred_*) can be ignored and honoring tx_st_ready is sufficient. The Hard IP performs the mandatory PCIe credit check on every TLP internally; if credits are short it blocks the TLP (and all following ones) and expresses that back-pressure solely by deasserting tx_st_ready. The flow control signals are needed to track credits to optimize the throughput, which is optional. 


    Regarding the credit limits, the Avalon-ST TX datapath does expose them. The six credit limit signals tx_cred_hdrfcp/datafcp, tx_cred_hdrfcnp/datafcnp, tx_cred_hdrfccp/datafccp carry the current per-type credit limits; the tx_cred_fchipcons strobes each credit the Hard IP consumes; and tx_cred_fc_infinite flags infinite types.


    Thanks. 

    Best Regards, 

    Ven