Forum Discussion
Yes, it takes 108 nsec before the first word read from DDR2 memory reaches your function. So if you require just one word, and you wait for each access to be finished before requesting the next it will take 108 + 12 nsec , or 8.33 MHz (max.). The idea is that you request either larger transfers (so the read latency gets less important) or if you have shorter requests that you pipeline them early to the HPC controller. The HPC will issue the read commands as early as possible and from the first word returned to the second word you will not see this read latency, but the actual delays between the read command issued to the DDR2 RAM (which could as little as 2 clocks if the next word requested is in the same row and bank as the previous). At some point row/bank switching and refresh will occur, making speed predictions a bit more difficult.