Hi,
Ok, I get better understanding on your TSE system setup now. You are basically doing the loopback connection on Avalon ST side instead of external loopback on your board.
In this case, you can separate the debug effort in following sequence.
- PC1 -> PHY0 -> TSE.Rx -> TSE0.Rx (avalon ST)
- I presume you still encounter intermittent error signal toggling where you may received wrong data at TSE0.Rx (avalon ST) ?
- You should be focus on fixing this error first else wrong data will be loopback to TSE1.Tx later
- Did you enable the TSE IP statistic counter setting to print out the report log ? Are we dealing with missing packet or just data error transfer ?
- Would you be able to perform loopback on the PHY chip to isolate is this PHY chip issue or FPGA TSE IP issue ?
- Have you tried switching the speed to 10M or 100M to see if the error signal still toggling ?
- I am not sure how your PC1 design looks like. Are you using your own Ethernet application software at OS level or just some Ethernet tester equipment ? Have you reviewed your PC1 setting (auto-negotation, speed or full/half duplex setting) or your OS level Ethernet driver to ensure there is no buffer overflow issue that may corrupt data packet transfer.
- Alternate option will be to switch to user other Ethernet packet generator. (For instance like using TSE1.Tx as source, then perform loopback on board to connect back to TSE0.Rx instead of using PC1 as source to isolate issue)
- TSE0.Rx (avalon ST) to TSE1.Tx (avalon ST) to TSE.Tx to PHY1 to PC2
- Once RX side issue is resolved then you can elaborate what's the issue on Tx side or maybe everything should be good once Rx issue is resolved.
Thanks.
Regards,
dlim
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