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GabrieleCoppolino's avatar
GabrieleCoppolino
Icon for New Contributor rankNew Contributor
6 years ago

C10GX and TSE with GXB transceivers

Hi all, I'm having some problems configuring the Triple Speed Ethernet core, working at 1Gbps, with a custom board with 6 transceiver channels (for now I'm trying to use 2 of them) connected to a Cy...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,

TSE IP itself already contains 8b/10b encoder/decoder so disable the 8b/10b encoder/decoder in NativePHY IP is correct way to go.

  1. Earlier you mentioned about a lot of char_err and disp_err issue. Is this issue resolved ?
  2. Now you mentioned obviously the exposed TSEs avalon-ST interfaces have been shortcircuited, but it's not working.
  • Can you explain further what do you mean by Avalon-ST intreface is short circuit ? What is short circuit and why are they short circuit ?
    • Also can you elaborate further what's not working here ?
  1. As for the panel_link doesn't assert high
  • Panel_link has its own version of definition depends on the mode setting as indicated in TSE user guide doc (page 119, table 73)
    • https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ethernet.pdf
    • But if panel_link stay zero highly indicate something wrong with Ethernet auto-negotiation (AN) process
    • Is your system setup trying to connect one TSE IP to another TSE IP ? If yes, then you need to configure one TSE IP into PHY mode AN while the other TSE IP into MAC mode AN
    • There are two auto-negotiation setting - PHY mode and MAC mode
    • PHY mode = the speed and duplex mode of our FPGA and external device will be resolved based on the value set in the dev_ability register. Meaning PHY mode is for advertise the link speed and duplex mode to the link partner
    • MAC mode is wait for the link speed and duplex mode from link partner and then resolve based on the link_partner ability register.

Thanks.

Regards,

dlim

GabrieleCoppolino's avatar
GabrieleCoppolino
Icon for New Contributor rankNew Contributor
6 years ago

Hi dlim,

>> 1. Earlier you mentioned about a lot of char_err and disp_err issue. Is this issue resolved ?

Now meantime I'm sending packets to the channel, led_connection_link is OFTEN high, until a led_connection_char_err (and consequently a led_connection_disp_err) occurs. Other led_connection_* signals are stable to '0', including led_connection_an (auto negotiation)

>>2.Now you mentioned obviously the exposed TSEs avalon-ST interfaces have been shortcircuited, but it's not working.

>> Can you explain further what do you mean by Avalon-ST intreface is short circuit ? What is short circuit and why are they short circuit ?

I used this therm improperly to indicate that:

tse0.tx <= tse1.rx

tse1.tx <= tse0.rx

where tse*.tx and tse*.rx are the avalon-st interfaces exposed by tse cores. Note that tse*.rx.ready and tse*.tx.ready are always '1'.

>>Is your system setup trying to connect one TSE IP to another TSE IP ? If yes, then you need to configure one TSE IP into PHY mode AN while the other TSE IP into MAC mode AN

My configuration is

......................................................FPGA

..................---------------------------------------------

pc1<-->| PHY0 <--> TSE0 <--> TSE1 <-->PHY1 | <-->pc2

.................|............... tbi...............a_st................tbi..............|

.................----------------------------------------------

note that i had to use dots instead of spaces