Hi,
TSE IP itself already contains 8b/10b encoder/decoder so disable the 8b/10b encoder/decoder in NativePHY IP is correct way to go.
- Earlier you mentioned about a lot of char_err and disp_err issue. Is this issue resolved ?
- Now you mentioned obviously the exposed TSEs avalon-ST interfaces have been shortcircuited, but it's not working.
- Can you explain further what do you mean by Avalon-ST intreface is short circuit ? What is short circuit and why are they short circuit ?
- Also can you elaborate further what's not working here ?
- As for the panel_link doesn't assert high
- Panel_link has its own version of definition depends on the mode setting as indicated in TSE user guide doc (page 119, table 73)
- https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ethernet.pdf
- But if panel_link stay zero highly indicate something wrong with Ethernet auto-negotiation (AN) process
- Is your system setup trying to connect one TSE IP to another TSE IP ? If yes, then you need to configure one TSE IP into PHY mode AN while the other TSE IP into MAC mode AN
- There are two auto-negotiation setting - PHY mode and MAC mode
- PHY mode = the speed and duplex mode of our FPGA and external device will be resolved based on the value set in the dev_ability register. Meaning PHY mode is for advertise the link speed and duplex mode to the link partner
- MAC mode is wait for the link speed and duplex mode from link partner and then resolve based on the link_partner ability register.
Thanks.
Regards,
dlim
New Contributor
