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GabrieleCoppolino's avatar
GabrieleCoppolino
Icon for New Contributor rankNew Contributor
6 years ago

C10GX and TSE with GXB transceivers

Hi all, I'm having some problems configuring the Triple Speed Ethernet core, working at 1Gbps, with a custom board with 6 transceiver channels (for now I'm trying to use 2 of them) connected to a Cy...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

HI,

NativePHY IP won't have TSE preset configuration as it doesn't support customized MII, GMII, RGMII or SGMII interface to connect with TSE MAC. This unique feature is provided by TSE IP itself.

I can see that you are setting TSE IP with MAC + PHY serdes interface option.

  • Your TSE IP error status signal indicate a lot of bit transfer error
  • I suggest you checkout below example design to learn how to build and configure TSE IP solution

TSE IP support 2 types of serdes interface in Cyclone 10 GX FPGA (Either LVDS or transcevier)

For LVDS variance (when you select LVDS IO in TSE IP transceiver type). Checkout

For transceiver variance (when you select GXB in TSE IP transceiver type). This is closer to your original intent. Checkout

Thanks.

Regards,

dlim

GabrieleCoppolino's avatar
GabrieleCoppolino
Icon for New Contributor rankNew Contributor
6 years ago

Hi dlim,

thanks for your reply.

I checked-out those projects which are a good source of informations.

However, I did not arrange a solution for me.

I'm able to connect two PHYs and see ethernet traffic in these situations:

  • Basic/standard PCS with 8B/10B encoder and decoder enabled, shortcircuiting the two interfaces (the situation I wrote in the initial post)
  • Basic/standard PCS with 8B/10B encoder and decoder disabled, shortcircuiting the two interfaces

In the second situation, PHYs have the 10bit tbi interface exposed. Disabling the transceiver option on the TSE, I got the same tbi interfaces (tx_d[9:0], rx_d[9:0], rx_clk, tx_clk). TSE is still configured 10/100/100 MAC + PCS with SGMII bridge enabled. This is the same configuration as in the second example you provided. Obviously the exposed TSEs avalon-ST interfaces have been shortcircuited, but it's not working.

In this situation tse_status_led_connection_link is high (but not the panel_link).