burst count

If I had to guess it is tracking how many outstanding reads are issued to the memory controller in terms of beats (words). So you can post read accesses to the memory and after a handful of clock cycles the read data returns. So this is a counter that is counting down by 1 when read data returns and counts up when 'size' (burst size) is issued.

It's common to build this type of logic into a read master in SOPC Builder/Qsys as well since you normally have a FIFO internally to catch the data so knowing how many reads are posted allows you to back pressure to avoid overflowing the FIFO.