burst count

The local_ready signal can be deasserted at times when the memory controller command queue is full. The queue can become full due to off chip refresh cycles or other commands being sent off chip that cause the queue to back up. A good example of this is if you attempt to perform a bunch of back to back reads or writes right after the memory controller comes out of reset. local_ready when the memory controller exists reset can be driven low after the command queue fills up for around 150us while the controller calibrates the interface.

This behavior has nothing to do with SOPC Builder or Qsys, this is just how the memory controller behaves. So if you instantiate the controller outside of SOPC Builder or Qsys it's still going to have this same behavior that you need to take into consideration in your mastering logic.

If you plan on implementing this outside of SOPC Builder/Qsys first then I recommend just using the Avalon-MM mode of the memory controller. This will make the transition easier since you'll be working with standard interfaces at that point. I believe in non-Avalon mode the memory controller uses interleaved address and data phases which you may find more difficult to work with as well. Make sure your logic throttles when local_ready is low otherwise your reads and write *will* fail.