burst count

OK，I just generate the 32bits write data , and the write_req is like this:

but I really don't understand why the simulation local_ready is period signal...

code:

always @(posedge clk or negedge reset_n)

begin

if (reset_n == 0)

begin

write_req <= 1'b0;

read_req <= 1'b0;

end

else if(local_ready)

begin

if((cycle_cnt >= 10'd1) && (cycle_cnt <= ({5'b0,{5{1'b1}}})))

write_req <= 1'b1;

else

write_req <= 1'b0;

end

else if (local_ready)

begin

if((cycle_cnt > {5'b0,{5{1'b1}}}) && (cycle_cnt <= 10'b1))

read_req <= 1'b1;

else

read_req <= 1'b0;

end

end

Thank you so much~~~