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I was testing the sample (
http://www.alterawiki.com/wiki/reference_design:_gen2x4_avmm_dma_-_arria_v) in the wiki in my Arria V starter kit, and tweaking a little the parameters (enabled bursting in BAR2) and initializing the onchip memory with some data.
I noticed that in the host PC, with a small Linux driver, half of the data read from the PCI bus memiory was repeated: of every 256 bytes, the second half was repeated from the first half.
The cause appeared when trying to run a simulation (lesson learned: always generante simulation files in Qsys and at least load the simulation), Modelsim complained with a compilation error. HPRxmReadData_i and other ports had inconsistent sizes (128 in Verilog Source, and 256 in the code generated by QSys).
The fix : in the file <quartus installation dir>\ip\altera\altera_pcie\altera_pcie_hip_256_avmm\pcie_256_avmm_port.tcl , look for the procedure add_pcie_hip_port_avmm_hprxmaster and change
set rxm_data_width 256
by
set rxm_data_width [ get_parameter_value DMA_WIDTH ]
Hope this helps
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Thanks for sharing this.
Honored Contributor
