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Altera_Forum
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15 years ago

Bug in tri_state_bridge implementation?

Hello everybody, It seems to me than I stumble on a bug in tri_state_bridge in Quartus v9.0: A simple master is connected to 16-bit SRAM through the tri_state_bridge. Only write bursts are...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Hello Ton,

The tri_state_bridge definitely supports burst accesses.

I've solved my problem by increasing width (N) of burstcount signal vector from 2 to 3 bits. The supported burst length is 2^(N-1) max. as defined in Avalon bus documentation.

regards,

fpga-dev