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Altera_Forum
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16 years ago

Bug in tri_state_bridge implementation?

Hello everybody, It seems to me than I stumble on a bug in tri_state_bridge in Quartus v9.0: A simple master is connected to 16-bit SRAM through the tri_state_bridge. Only write bursts are...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

I don't think the 3-state brigde supports burst-mode.

In burst mode the master set the address and the burstcount just once and the slave is supposed to increase the internal address every access.

-- Ton