Bug in Stratix III altlvds?

Hi everybody,

I am trying to set up a lvds receiver with external PLL in a Stratix III device using the megawizard and altlvds function.

Configuring altlvds as receiver + external PLL + DPA works fine, but if a make a analysis and syntheses in Quartus 8.0 SP1, i get the following error:

"Error: The port rx_syncclock (which is the slow clock from PLL running at data rate/DESERIALIZATION_FACTOR) must be connected to use the rx_dpa_locked port when the USE_EXTERNAL_PLL parameter is set to ON"

I read several manuals and figured out, that the rx_syncclock is mandatory if external PLL with DPA is used. But the megawizard is not instantiaing this port!

If I add this port manually, the error message disappears.

Could anyone please confirm the megawizard misbehaviour?

thanks in advance,

lestard