Forum Discussion
ContributorBug in Avalon-MM PCIe core for Non-Qword aligned writes
- Hi,
I see the misunderstanding. BAR 32/64-bit setting refers to address width. Data width is the native master width, can be 64 to 256 bit, in your design 64 bit. To see address and data presented to a 32-bit slave, tap the slave interface directly.
Regards,
Frank
Super Contributoron the 64 bit BAR2 interface, address bits 2:0 are always zero, the interface can only perform aligned access. Unaligned accesses from the host are translated to aligned accesses by shifting data and setting byte enables. When connecting 64 bit BAR2 to 32 bit slaves, interconnect will take care of the back-translation.
Do you see wrong data in 32 bit slave access?
Regards,
Frank
ContributorHello,
I have both BAR0 and BAR2 set to 32-bit as below:
So based on this:
I had expected it to accept a DWORD aligned address.
The data itself is ok in all cases.
Thanks
- FvMHi,
I see the misunderstanding. BAR 32/64-bit setting refers to address width. Data width is the native master width, can be 64 to 256 bit, in your design 64 bit. To see address and data presented to a 32-bit slave, tap the slave interface directly.
Regards,
Frank- corestar
Hello @FvM ,
You are right, I did misread that. I had made my bridges 64-bit data width since I assumed they had to be in order to connect to the 64-bit wide PCI data. Just to see what would happen, I changed them to 32-bit and it works! Non-qword aligned 0xC shows up in the address and 0x80 in the data.
I don't quite see how a 64-bit interface can feed a 32-bit interface at the same clock speed. What if the TLP had 20 dwords? I assume Qsys is creating a FIFO somewhere, but using the technology viewer proved an exercise in futility.
It's all a bit confusing, but at least I'm a step closer.
Thanks for the help.
