BUG - Fir filter coefficient read mode

Hi Erich, Thanks for your update. Regarding the output valid, if I understand your correctly, you are referring to the coeff_out_valid signal. For your information, per the observation in my simulation and signatap, this signal will be high one cycle after there is a valid coeff address fed to the coeff_in_address input to indicate there is a valid coeff data at coeff_out_data output. In the recent simulation and signaltap screenshots from me, you can observe that the coeff_out_valid = low when there are invalid address ie -5, -4. The coeff_out_valid goes high one clock cycle after there is a valid address ie 0, 1, 2 ... Please feel free to let me know if there is any further concern. Thank you. Best regards, Chee Pin