BUG - Fir filter coefficient read mode

Hi Erich, Thanks for your update. From my previous simulation, seems like there is only one clock cycle latency from the address changes to coeff data available at the out_data instead of the 3 clock cycles shown in the user guide. Just wonder if you are referring to this difference? If not, please feel free to further elaborate so that I could highlight to Factory for documentation update. Please let me know if there is any concern. Thank you. Best regards, Chee Pin