Hi Erich,
Just to update you on my recent finding after running hardware test and simulation. For your information, with my simple test design, I can get the same observation in both hardware and simulation. One thing that I notice is that it seems like we do not need to assert the read signal to retrieve the coefficient value at a specific address. With the coeff_in_areset = 0, as long as your address is a valid value, then the coeff_out_valid = 1 and coeff_out_data will show the coefficient data at that address. When I change to different valid address, the right coefficient data is output. There is one clock cycle latency from address change to the coefficient data available at the out_data. This tallies between simulation and hardware.
Note that I am using Q18.1Pro with A10. Since you are observing differences between hardware and simulation with previous Quartus version, I would like to recommend you to use the latest Q18.1Pro where I observe consistent functional behavior between the simulation and hardware.
Note that it seems like I am unable to attach the screenshot to this post. Will try to email you the screenshot.
Please let me know if there is any concern. Thank you.
Best regards,
Chee Pin
Occasional Contributor
