Honored Contributor
Honored ContributorHi all, i am stillan FPGA noob and i have a similar problem, and it is about bandwidth calculations but using a SDR sdram.
I hope someone could help me. My video input into the deinterlacer and the framebuffer are respectively 320*240i (5 bits per color plane) and 320*240p(5 bits per color plane). Deinterlacer performs only bob with no buffering, and frame buffer performs triple buffering. My SDR SDRAM controller settings are clock 100MHz, word width 16bits, fifos 64 bits and burst target 16 bits. color planes are in parallel, and I've calculated that i need a bandwidth of 320*240*15(pixels)*50(fps)*6(a read master and a write master for each buffer)= 345.6mb\s while my available bandwidth is 16bits*100MHz= 1.6gb/s I set my avalon MM masters port width to 16, fifo depth to 64 and interface burst target to 16 both for write only and read only masters interface. CVI fifo is set to 720, cvo to 640, but the entire system doesn't work properly, I still have an input overfolw. I think the problem could be accord to bandwidth calculations.. or the settings for the memory mapped itnerfaces are wrong.. I REALLY don't know how to handle all this, any hint would be precious. One last consideration: at the end off all, BEFORE the frame buffer,i have a Scaler. Maybe it is it that stalls my video flow? best regards Phate
