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1 - Make sure your timing is properly constrained and that you are meeting timing requirements.
2 - If I understand correctly, you've got a 64-bit DDR2 interface. How wide is the local interface with the Microtronix controller. Make sure all the memory masters on your frame buffers are set to match that width. Also, make sure your burst targets are set to at least 32.
3 - You should get the design working with one video processing path first. Then add to it.
Jake
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Hi Jake
Yes you are right, the DDR2 has 64 DQ lines and the local interface of all the frame buffers to the DDR2 controller is 128 bit wide.
I have set the following parameters for the all the frame buffers:
1. Master READ/WRITE interface width: 128
2. Master READ/WRITE FIFO Depth: 1024
3. Master READ/WRITE Burst Target: 128
The Microtronix DDR2 controller has 2 settings for each port, which is
fifo depth and
burst length. I have set them to be 512 each. Do you think that the burst length should be less than FIFO depth?
You said that "
you should get the design working with one video processing path first. then add to it".
I assume that by video processing path you mean CVI and CVO blocks (excluding frame buffers). Can I directly connect these two? I previously tried that but it did not worked. I read in some thread here that it might not work. However I can just put in a scaler with scaling factor of 1 just to delay the data. I hope it wont create any timing violations.
Regards
Faisal
Honored Contributor
