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Altera_Forum
Honored Contributor
16 years ago --- Quote Start --- Some other random thoughts: Do you even need to convert between clocked and avalon streaming video multiple times? Could your custom video IP be adapted to process the avalon stream directly? It would simplify your system a lot if you only had one CVI and one CVO to worry about. Do you even need all the frame buffers? Just based on your block diagram, I see no purpose for the first frame buffer. Unless the custom video IP needs to see the video from different delayed time points, I don't really see what the other frame buffers are for either. As your video IP is running at 166MHz and your memory at 300MHz, are you doing anything to address potential clock domain crossing issues? The default clock domain crossing logic in SOPC builder can be quite inefficient. You may need to explicitly add a pipeline bridge. --- Quote End --- Hi Kevin Thanks for the advice. You got it right, I am using three frame buffers because the custom video processing block is actually using delayed version the frames. It looks at a particular pixels in the current frame in two previous frames to find out the correlation between the time delayed values of the pixels at the same positions in previous two frames. That is why I am using three frame buffers. For the clock domain crossing, I inserted pipeline bridges in the previous version but I still had some problems. I will put them back in and see what happens now. As I told that there are six read and write ports in three frame buffers, should I put pipeline bridge for all these six ports? I was assuming that SOPC will automatically see the CDC and put the bridges but I think its much better that I do it myself. About the buffer sizes in CVI and CVO modules, I am using 4096 pixel buffers each. I get underflow only from the video_out_f2 (the last module) so I increased its FIFO size to 4096 pixels which should be good enough for at least two lines of 1080p video. Regards Faisal