Honored Contributor
Honored ContributorThe spreadsheet was posted in this thread:
http://www.alteraforum.com/forum/showthread.php?t=6841 What value did you use for the size of the read/write master ports of the frame buffers? With a master data port of 64-bit and R:G:B in parallel, the packing of pixels into memory word is really inefficient with only 2 pixels per 64-bit word (see wasted bits in the spreadsheet). I am not familiar with the Microtronix memory controller so this could make things worse but if your local Avalon-MM bus is currently 64-bit wide then perhaps you could try increasing it to 128 and either reconfigure the local interface of your controller or see if SOPC Builder can handle the switch fabric? Timing closure could be harder and you could waste logic but this would at least take you down from 25% to 7% waste. Using double buffers for the second and third paths should be fine in your design. I think they are not even needed in this case so you could consider removing them to test whether memory bandwidth is really the issue.
