Buffer Overflow and Underflow in Clocked Video Input/Output

Hi all

Thank you very much for your valuable suggestions. I really appreciate your help.

I have attached top level diagram with this message. A picture worths thousand words. Please have a look at attached .JPG file.

bandwidth calculations:

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First about the bandwidth calculation. I have DDR2 memory with 64 bit data line (DQ). Input is 1080p 60fps in RGB 4:4:4 (24 bits or 3 bytes) format. It translates to approximately 148.5 MHz input rate with 24 bit video data.

Since I have three frame buffers in my design, there are total of 6 read and write ports. So

input rate = 148.5MHz * 3 bytes * 6 ports = 2.673 GBytes/sec

There are 64 DDR2 data lines (8 bytes), with data being read/written on both clock edges and assuming 75% availability of DDR2 memory. The DDR2 controller runs at 300 MHz clock. Therefore

memory bandwidth = 300MHz * 8 bytes * 2 * 0.75 = 3.6 GBytes/sec

So I think memory bandwidth is enough to handle three HDMI streams. I could not find the bandwidth calculation sheet. So please send me the link or reply with attachment.

constraints:

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For constraints, I added video_input.sdc and video_output.sdc. I will add video_buffer.sdc and do the synthesis again. For other constraints, I just defined the clocks, derive_pll_clocks command and set a few paths as false paths which I am sure of. I am using Microtronix DDR2 controller which generates its own SDC file which I have included in the design as well.

I haven't set input and output delays on video signals because I am not sure how to calculate them. Please let me know of any other constraints that I should create.

In the top level diagram, "frame_buffer_f0" uses tripple buffering and other frame buffers use double buffering. Should I set them to use tripple buffering as well?

Input and output frame rate are not an issue in my design. I dont want any frame rate adaptation. I tried to use the recovered hdmi clock (hdmi_rx_clk which is approx 148.5MHz) for all three video_input and video_output modules but I did not get any output. So I generated a local 148.5 MHz clock from PLL (hdmi_syn_clk) which is used in video_input and video_output modules as shown in attached diagram.

I hope I did not bored everyone with these details. I'll appreciate your suggestions and help.

Regards

Faisal