Bonded Mode support for GXT transceivers in L-tile stratix 10 FPGA

Hi Nathan,

"This could be because you data rate is lower allowing Quartus Prime Pro to used x6 or x24 clock line. If your data rate is higher than 17.4Gbps, then this is because the Native Phy IP System Messages does not error this out. You will need to perform full compilation to observe error in fitter."

You are right. I get the error while configuring the ATX PLL with master CGB

Also, I am seeing same behaviour for an H-tile device also.

I think even H-tile transceiver doesn't support x2 bonded mode for more than 17Gbps.

The reason being, I created the project for H-tile S-10 FPGA (1SX280HUF50E1...) and in the platform designer I am getting the error " Master CGB input clock frequency (9667.96875MHz) is above maximum allowed (8700MHz).

So, my conclusion is either L-tile or H-tile XCVR doesn't support x2 bonded mode for more than 17Gbps link rate.

With Regards,

HPB