Forum Discussion
Altera_Forum
Honored Contributor
8 years ago --- Quote Start --- What kind of errors? --- Quote End --- Hello Steve, Qsys says it is missing the address write and write data channels. It's perfectly legal to create an AXI component that just writes or just reads. So this should not be an error. I added the address write and write signals and tied off the outputs driving the rest of the AXI interconnect. Cheers, Tom