Avalon to Onchip RAM Bridge

I am have very simple microcontroller based on the Nios II/e. There is no cache, no MMU and no OS. The new code image is downloaded by the Nios using an API to a board level processor who's Flash contains code images for all programmable conponents on the board.

I spent about an hour and a half in a WebEx session with an Altera FAE and he found the problem. I constructed my bridge with the SOPC Builder Component Editor. I used the typical slave template and the typical master template and connected them back-to-back. As it turns out, the slave template uses a word address bus and the master template uses a byte address bus. Once the differences were accounted for, everything works as expected.