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Altera_Forum's avatar
Altera_Forum
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16 years ago

Avalon to Onchip RAM Bridge

I currently am running a Nios II system based on SOPC Builder with separate RAM & ROM banks comprised of onchip memory. I have a requirement to update the the software while the system is running. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Are you only have 1 Nios II CPU in your system?

My understand on your requirements is:

(1) Nios II is requested to load a new software.

(2) In the background, Nios II enter software loading routine, read the binary data from a source and write it to the ROM. In the foreground, Nios II still running normally? (So, you are running on an OS?)

(3) Once writing finish, trigger a reset to the system (or just the Nios II), new software will be loaded from ROM to RAM, and Nios II start running with new software from RAM.

Question:

(1) How do you update the data in your onchip memory ROM?

(2) Do you still need you foreground software to be functioning while background is loading new software into the rom.

Answer to your question:

(1) 32 bit wide memory is being byte addressed four times with incrementing byte addresses.

Ans: This is always be the case, since Nios II have Instruction cache, and the cache line size is always 32bytes = 4 word. Whenever there is a miss on the instruction cache, Nios II is going to load the full 4 words to fill up the line. Why this is an issue for your system?