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Altera_Forum
Honored Contributor
16 years agoAvalon Streaming Interface with FIR
I have the following outputs from an FIR I’ve got a question relating to the FIR compiler 9.1. The picture shows Source_Valid Source_SOP Source_EOP Source_Channel Source_Ready is ...
Altera_Forum
Honored Contributor
16 years agoIt is only one clock cycle. Both SOP and EOP must be qualified with VALID. so real_eop = eop & valid.
Jake