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Honored Contributor
Honored ContributorAvalon Streaming Interface VHDL templates
Has anyone got any Avalon Streaming Interface VHDL templates? I want to interface an A/D to an FIR to an avalon memory interface. thanks
Altera_ForumHonored Contributor
Honored ContributorIt is very difficult to answer you on two different threads. Just pick one.
Valid should be high for one cycle only if Ready is asserted. If not you must wait until it is.
