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Altera_Forum
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16 years ago

Avalon Streaming Interface VHDL templates

Has anyone got any Avalon Streaming Interface VHDL templates? I want to interface an A/D to an FIR to an avalon memory interface. thanks
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

to read from a dual channel FIR, multi-cycle (7 clocks) is the following correct,

ch1:

ast_SOP=1 AND ast_VALID=1

ch2

ast_EOP=1 AND ast_VALID=1

VALID will only be high for one clock cycle