Avalon St IPs "firstSymbolInHighOrderBits" parameter

Pretty much *all* of the Av-ST Altera IP cores work on having the first symbol in the upper bits. So if possible you should to so as to make things easier.

If your core has only one symbol per beat (i.e. the data symbol width is equal to the data bus width), then you just need to set the "firstSymbolInHighOrderBits" parameter on the interface to be "true" - doing so in this case will not change anything.

If the core has multiple symbols per beat, it can be a little trickier. But there are three options:

1) you redesign the logic with the first symbol in the upper bits.

2) you leave the logic the same, but add a simple remapping to the input and output port, for example in Verilog:

genvar idx;
generate for (idx = 0; idx < NUMBER_OF_SYMBOLS; idx=idx+1) begin : remap_loop
    localparam newidx = NUMBER_OF_SYMBOLS - idx - 1;
    assign external_src_data = internal_src_data;
    assign internal_snk_data = external_snk_data;
end endgenerate

That will add no additional logic in the final design (it just rearranges the bus) and allows you to set the "firstSymbolInHighOrderBits" parameter set to "true" without having to redesign any of your internal logic. In fact if you are using the core for other things as well as Qsys, you can control the above using a parameter:

genvar idx;
generate if (FIRST_SYMBOL_IN_UPPER) begin
    for (idx = 0; idx < NUMBER_OF_SYMBOLS; idx=idx+1) begin : remap_loop
        localparam newidx = NUMBER_OF_SYMBOLS - idx - 1;
        assign external_src_data = internal_src_data;
        assign internal_snk_data = external_snk_data;
    end 
end else begin
    assign external_src_data = internal_src_data;
    assign internal_snk_data = external_snk_data;
end endgenerate

3) I believe there is an Avalon-ST data format adapter core. I can't remember off the top of my head, but this may provide the capability of doing the above remapping. You instantiate an instance of the format adapter and match the "source" setting to your modules source, and the "sink" setting to the demultiplexer cores sink. The module then handles the adaption. The downside of this compared to (2) is you end up having to instantiate multiple copies of the format adapter which can be a pain.