avalon-mm pipelined read completion order

Replying to myself here because I found something interesting...

It seems that this is a real issue with Avalon-MM. In fact, the code that generates the arbitration logic (quartus/sopc_builder/bin/europa/e_ptf_slave_arbitration_module.pm) has a routine to deal with this problem: sub _ensure_latent_master_reads_coherently at line 5850 in 9.1. However, this code only deals with fixed-latency slaves. The problem is that my system has one fixed and one variable-latency slave, so it is difficult to tell if two reads will complete correctly because you never know on what cycle the variable-latency slave will assert readdatavalid. Probably the cleanest fix would be for the arbiter to always assert waitrequest if a master attempts to switch slaves while reads are still outstanding to the variable-latency slave.

I implemented a bridge component to do exactly this and it seems to fix the problem, but it is a total hack (relies on knowledge and careful design of memory map). I guess I will be contacting Altera directly.