Honored Contributor
Honored ContributorThanks for the great explanations and suggestions...
Originally I had my memory and SOPC components running on the same 133 MHz clock. I created a second clock to run the SOPC components at 100 MHz and kept the memory attached to the 133 MHz clock. I tried to change the memory port width to 16 as suggested but the SOPC builder would not save the values. I did not get any errors or warnings, it just displayed the original values the next time I opened SOPC builder. VGS's post cleared up that mystery, I am running 8 bit RGB in parallel. I set the Port width to 32 and the fifo depths to 256 and left the burst targets at 32. Settings are saved but my video is torn across the display. When I set the port width to 256 and leave the fifo depths and targets at their defaults I get good video. Since I appear to be approaching a memory bandwidth issue does it make sense to place my frame buffer directly after my CVI (8 bit 2 color plane in seq) and do the color space conversion downstream from the frame buffer? I've never gotten a warm fuzzy about when a frame buffer is necessary. It is obvious to me that there would need to be one between my CVI and CVO due to the rate conversion but is it necessary between certain VIP components? On that note, I've also questioned the clock rate for the VIP components. I've read that it needs to be at least the rate of the input pixel clock but what if the stream is resequenced from sequential to parallel or vice-versa? Sorry for the newbie questions... and thanks for all the help
