Avalon-MM master interface on Frame Buffer

Hello,

Write and read bursts to and from the memory cannot be interrupted and there is no guarantee that the data can be streamed as fast as it go or come back from the memory. Consequently, the write master is using a FIFO to buffer a sufficient amount of data before it issues a write burst and the read master is using a FIFO to store the data received during a read burst. The fifo depth parameters control the sizes of these two FIFOs. The burst target parameters define the typical size of a burst. The default values are appropriate for most video systems.

If you are using SOPC Builder, the tool will build the switch fabric for you and there is no need to use 16 for the memory port width. Using a larger number (eg, 128 or 256 bits) will probably improve things. You should also try to run the memory at a faster speed than the rest of the design to squeeze more bandwidth (tick the "use different clocks" checkbox in the two frame buffers) .

vgs