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Altera_Forum's avatar
Altera_Forum
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15 years ago

Avalon mm master burst issue (SGDMA)

Hi everybody,

I am working on the SGDMA IP in order to transfer data between PC and on-chip memory.

I enabled burst transfers in parameters settings of SGDMA. When I'm trying to do burst write (on "on-chip RAM") with longer data size than maximum burst size, there is a problem with the write address (In my example "write burstcount signal width " = 8).

The DMA write block is doing correctly the data transfer but between two burst packets the write address return to base address instead of continue with the previous one.

With SGDMA burst read operations there is no problem, adress increments correctly between two burst packets.

Is it not possible to write longer burst data size than the SGDMA burst size?

Thank you for your help! :)

Tonio

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    In fact there is a bug in version 9.0, the SGDMA will split the packet but the address not increase (with master read and write). This issue has been fixed in version 9.1 and 9.1 SP1.