avalon mm byte enable

In the project we are currently working on, we want to read and write pixels to external DDR SDRAM.

We need to be able to use byte-mask / byte-enable bits to not overwrite some previously written good

pixels, for writes that are not aligned.

Now, I just recently learned that the Altera mm-interface does not support arbitrary byte enable masks,

it only supports:

(from www.altera.com/literature/manual/mnl_avalon_spec.pdf page 15)

The following values are legal for a 32-bit slave:

1111 writes full 32 bits

0011 writes lower 2 bytes

1100 writes upper 2 bytes

0001 writes byte 0 only

0010 writes byte 1 only

0100 writes byte 2 only

1000 writes byte 3 only

The point I am getting at is this:

I have 8, 16, and 24 bit pixel data I would like to write to an arbitrary byte-address. In order to do this

with Avalon right now, I must read a complete aligned data word,

modify only the data I am interested in, then write the full word back to main memory.

If my mm data width is 32 bit and I want to write only the top two bytes,

I can't use the byte mask 1100, according to the above.

Is there any trick to handling this, without having to read the full data word,

modify the desired bytes, then write the full thing back?

Can the mm-master data port that is controlling the mm-slave port on the DDR controller

be made smaller DDR controller's native width, and thus cause all addresses to be aligned? In other

words, if I want to write 8 bit words, can I address the memory in this fashion, and bypass the need for

write enables all together?

What is the reason for not supporting arbitrary byte-enable patterns, when they are inherently supported by external SDRAM?