avalon mm byte enable

On reads the master most likely asserts all the byte enables and filters out the extra data that returns. So if you read from 0 followed by 2 I would expect two 16-bit reads for each access by the master. So for the read at address 0 I would expect word 0 and 1 to be read from the slave and the master will ignore the upper 16-bits that returns. Likewise for the read at address 2 I would expect word 0 and 1 to be accessed again only the lower 16-bits will be thrown out. I hope that made sense, this is usually easier to show using pictures.....