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nelky's avatar
nelky
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

avalon_master_waitrequest signal is always high

Hi, I am creating a project using Quartus Prime Pro on AGFB022R25A2I3V to read and write to single-port on-chip RAM. When I tried to simulate using modelsim, I found that the avalon_master_waitrequ...
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ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
1 year ago

Hi,


May I know in your design which ip (avalon-mm master) is interfaced with this on-chip memoery II (RAM or ROM) Intel FPGA IP? I think avalon_master_waitrequest is a signal of the avalon-mm master.

Are you using BFM simulation?

Possible to provide the on-chip memoery II .ip file for checking the settings?


Thanks,

Regards,

Sheng


nelky's avatar
nelky
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

Hi ShengN,

I created the master myself. After checking, I found that the avalon_master_waitrequest at the master side is an input pin. It gets the signal from altera_mm_interconnect_1920_haeydly uav_waitrequest pin. But this pin somehow stays high forever. Do I miss out anything here?

Regards