Forum Discussion
New ContributorAvalon Dual-Master Bus with constant waitrequest on connection point
That's correct. Your master can initiate a transaction to a slave when wait request is asserted.
Actually wait request asserted is the default condition also if no transaction is on going in most of slave IP and interconnect.
When your master start the transaction you put on the bus address/cmd/data and must keep all stable until the wait request signal is deasserted. cmd = read or write
This is all reported in the Avalon specification.
If you look into the "Typical Read and Write Transfers" chapter here you can immediately read it in the note:
"waitrequest can be decoupled from the read and write request signals. waitrequest may be asserted during idle cycles. An Avalon® -MM master may initiate a transaction when waitrequest is asserted and wait for that signal to be deasserted. Decoupling waitrequest from read and write requests may improve system timing. Decoupling eliminates a combinational loop including the read, write, and waitrequest signals"
This explains what you see and your logic shall cope with that.
Hope it helps
Frequent ContributorHi Sir,
Can you re-send the attachment so that I can take a closer look? I am not able to view it as it is corrupted.
Regards,
Aida
New ContributorSorry for taking so long to reply, hopefully it's not to late.
Attached is an example of a dual avalon master setup, now using a cyc5 + on chip memory instead of the stratix 10. But it behaves the same.
When using 2 masters on the slave the slave will continously out put waitrequest high, but after asserting read/write on one master the signal will goes low during the transfer.
So the transfer works, I just wonder is this waitrequest=high in idle normal for multimaster setups?
Marco_IntelThat's correct. Your master can initiate a transaction to a slave when wait request is asserted.
Actually wait request asserted is the default condition also if no transaction is on going in most of slave IP and interconnect.
When your master start the transaction you put on the bus address/cmd/data and must keep all stable until the wait request signal is deasserted. cmd = read or write
This is all reported in the Avalon specification.
If you look into the "Typical Read and Write Transfers" chapter here you can immediately read it in the note:
"waitrequest can be decoupled from the read and write request signals. waitrequest may be asserted during idle cycles. An Avalon® -MM master may initiate a transaction when waitrequest is asserted and wait for that signal to be deasserted. Decoupling waitrequest from read and write requests may improve system timing. Decoupling eliminates a combinational loop including the read, write, and waitrequest signals"
This explains what you see and your logic shall cope with that.
Hope it helps
