Audio Extract MegaCore

i'm sure that must be a typo and its meant to say I2S

on the other hand that is the only reference to I2S in the documentation. on page 93 of the SDI UG, it says the SDI cores use the AES standard, so i'm not sure why the document shows I2S as well. you might file an SR to get clarification

i don't think converting AES to I2S should be too tough if that's where you end up

No reply from Altera yet (great support guys!)

However, I am still trying to implement audio extraction, but it doesn't work.

I provide the audio extract core with vid_data, vid_clk, vid_data_valid signals (manual table 4-10), but no output is available. Since I don't need RAM, error or any other status/control/etc registers, I don't use reg_clk input to provide clock to that input.

The "include clock" option is also off, so I don't use fix_clk signal, because there are no fee PLLs left for 200MHz clock. This means, that I have to use aud_clk signal feeding it with 3.072MHz signal.

However, when all resets are tied to 0, all video signals are OK and 3.072MHz is provided, there are no output signals. What did I forget?

I will respond to my thread once again, for people facing same problems in the future.

The audio extract and audio embed cores both support I2S, AES and parallel input audio (I've managed to find out that myself).

It is better to use fix_clk option, but if You have 3.072MHz clock signal + data sync to video - both cores works without fix_clk.

reg_clk signals can be left unconnected, if You don't use status and control registers.

Those new schematic symbols for both cores are weird and it is hard to understand which pin is input and which is output.

Altera didn't bother to respond to service request yet :)

Hi Socrates

May I ask you a question about the output of SDI extractor?

The SDI extractor has three outputs - aud_ws, aud_data, aud_clk_out.

Are these three signals I2S signals?

(I've searched keyword I2S in SDI user guide and cannot find it)

If so, I think I can set these three signals as output pins and connect to some audio processing IC.

Thanks.

Yes.

I2S is not mentioned in the datasheet because Altera didn't make this core. It was developed by a 3rd party company and later sold to Altera afaik.

--- Quote Start ---

I will respond to my thread once again, for people facing same problems in the future.

The audio extract and audio embed cores both support I2S, AES and parallel input audio (I've managed to find out that myself).

It is better to use fix_clk option, but if You have 3.072MHz clock signal + data sync to video - both cores works without fix_clk.

reg_clk signals can be left unconnected, if You don't use status and control registers.

Those new schematic symbols for both cores are weird and it is hard to understand which pin is input and which is output.

Altera didn't bother to respond to service request yet :)

--- Quote End ---

Did Altera finally responded to SR? If Yes, then what was the answer?

Did You finally managed to make it work?